TMDXEVM5515【PDF 90/159 页】EVAL MODULE DSP FOR C55XX

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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013

Additionally, the SDRAM/mSDRAM interface of EMIF supports placing the SDRAM/mSDRAM in "Self-

Refresh" and "Powerdown Modes". Self-Refresh mode allows the SDRAM/mSDRAM to be put into a low-

power state while still retaining memory contents; since the SDRAM/mSDRAM will continue to refresh

itself even without clocks from the DSP. Powerdown mode achieves even lower power, except the DSP

must periodically wake the SDRAM/mSDRAM up and issue refreshes if data retention is required. To

achieve the lowest power consumption, the SDRAM/mSDRAM interface has configurable slew rate on the

EMIF pins.

The device has limitations to the clock frequency on the EM_SDCLK pin based on the CV DD and

DV DDEMIF .

5.9.3

?

?

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The clock frequency on the EM_SDCLK pin can be configured either as SYSCLK (DSP Operating

Frequency) or SYSCLK/2 via bit 0 of the ECDR Register (0x1C26h)

When CV DD = 1.3 V and DV DDEMIF = 3.3 V, 2.75 V, or 2.5 V, the max clock frequency on the

EM_SDCLK pin is limited to 100 MHz (EM_SDCLK ≤ 100 MHz). Therefore, if SYSCLK ≤ 100 MHz, the

EM_SDCLK can be configured either as SYSCLK or SYSCLK/2, but if SYSCLK > 100 MHz, the

EM_SDCLK must be configured as SYSCLK/2.

When CV DD =1.05 V, and DV DDEMIF = 3.3 V, 2.75 V, or 2.5 V, the max clock frequency on the

EM_SDCLK pin is limited to 60 MHz (EM_SDCLK ≤ 60 MHz). Therefore, if SYSCLK ≤ 60 MHz, the

EM_SDCLK can be configured as either SYSCLK or SYSCLK/2, but if SYSCLK > 60 MHz, the

EM_SDCLK must be configured as SYSCLK/2.

When DV DDEMIF = 1.8 V, regardless of the CV DD voltage, the clock frequency on the EM_SDCLK pin

must be configured as SYSCLK/2 and ≤ 50 MHz.

EMIF Peripheral Register Descriptions

Table 5-11 shows the EMIF registers.

Table 5-11. External Memory Interface (EMIF) Peripheral Registers (1)

HEX ADDRESS

RANGE

1000h

1001h

1004h

1005h

1008h

1009h

100Ch

1010h

1011h

1014h

1015h

1018h

1019h

101Ch

101Dh

1020h

1021h

103Ch

1040h

1044h

1048h

ACRONYM

REV

STATUS

AWCCR1

AWCCR2

SDCR1

SDCR2

SDRCR

ACS2CR1

ACS2CR2

ACS3CR1

ACS3CR2

ACS4CR1

ACS4CR2

ACS5CR1

ACS5CR2

SDTIMR1

SDTIMR2

SDSRETR

EIRR

EIMR

EIMSR

REGISTER NAME

Revision Register

Status Register

Asynchronous Wait Cycle Configuration Register 1

Asynchronous Wait Cycle Configuration Register 2

SDRAM/mSDRAM Configuration Register 1

SDRAM/mSDRAM Configuration Register 2

SDRAM/mSDRAM Refresh Control Register

Asynchronous CS2 Configuration Register 1

Asynchronous CS2 Configuration Register 2

Asynchronous CS3 Configuration Register 1

Asynchronous CS3 Configuration Register 2

Asynchronous CS4 Configuration Register 1

Asynchronous CS4 Configuration Register 2

Asynchronous CS5 Configuration Register 1

Asynchronous CS5 Configuration Register 2

SDRAM/mSDRAM Timing Register 1

SDRAM/mSDRAM Timing Register 2

SDRAM/mSDRAM Self Refresh Exit Timing Register

EMIF Interrupt Raw Register

EMIF Interrupt Mask Register

EMIF Interrupt Mask Set Register

(1)

Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable

word accesses to the EMIF registers.

90

Peripheral Information and Electrical Specifications

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